Abraham



G. ABRAHAM Re. 25,087

SOLID STATE DEVICE AND METHOD OF MAKING SAME 2 Sheets-Sheet 1 Nov. 21,1961 Original Filed June 11, 1957 Ill-51L EE J R JEH SWEEPER 2% I 22 i0.0. POWER su PP LY SOURCE OF DYNAMIC B+ POW ER 1 000' SUP PLY pfs PfsELE'LE INVENTOR GEORGE ABRAHAM MAM MW ATTORNEY Nov. 21', 1961 G. ABRAHAM7 SOLID STATE DEVICE AND METHOD OF MAKING SAME Original Filed June 111957 2 Sheets-Sheet 2 INVENTOR GEORGE ABRAHAM fiwv X WAGEMT BY ATTORNEYUnited States Patent Otlfice Re. 25,087 Reissuecl Nov. 21, 1961 (Grantedunder Title 35, US. Code (1952), sec. 266) Matter enclosed in heavybrackets appears in the original patent but forms no part of thisreissue specification; matter printed in italics indicates the additions'made by reissue.

The invention described herein may be manufactured and used by or forthe Government of the United States of America for governmental purposeswithout the pay- 'ment of any royalties thereon or therefor.

This invention relates in general to the manufacture of solid statedevices and in particular to the forming of a semiconductor signaltranslator.

In the prior art, the electrical characteristics of solid state deviceshave been controlled by forming. Solid state devices, for example, havebeen formed to control their impedances so that they will have improvedperformance in electrical amplifier and rectifier circuits. Heretofore,however, it has not been possible to form solid state devices so thattheir voltage-current characteristics curves would have a plurality ofnegative resistance regions at selected potential levels.

In accordance with the foregoing, it is an object of the presentinvention to provide a solid state device having a voltage-currentcharacteristic that includes a plurality of negative resistance regions.

Another object of the present invention is to provide a method offorming solid state devices in. which a predetermined small quantity offorming energy is applied to a solid state device to provide thevoltage-current characteristic of the solid state device with a negativeresistance region.

Another object of the present invention is to provide a method offorming solid state devices in which a series of small quantities offorming energy is applied to an electrode of a solid state device and isinterrupted when the voltage-current characteristic of the deviceacquires a negative resistance region.

Another object of the present invention is to provide a method forforming a solid state device in which a source of dynamic B+ is appliedto the body of the device and in which a series of small quantities offorming energy is applied to an electrode of the device and isinterrupted when the voltage-current characteristic of the solid statedevice has acquired a desired negative resistance region. Another objectof the present invention is to provide a method of forming a solid statedevice in which a source of dynamic B+ is applied to the device totemporarily remove previously formed negative resistance regions fromthe voltage-current characteristic of the solid state device while aseries of small quantities of energy is applied to the device to providean additional negative resistance region in the voltage-currentcharacteristic. 7

Another object of the present invention is to provide a solid statedevice having a body of a first type of semiconductor material in whichparticles of a second type of semiconductor material have been dispersedin discrete zones in the latice of the body to form p-n junctions.

Other objects and many of the attendant advantages of this inventionwill be readily apparent as the same becomes better understood whenconsidered in connection with the accompanying drawings in which:

level.

for a particular solid state device including a negative resistancecharacteristic provided in accordance with the instant invention.

FIG. 5 is the voltage-current characteristic of a solid state device inwhich a steady state of electrical charge carriers have been stored, thesteady state having a magnitude such that the device acquires a negativeresistance characteristic.

FIG. 6 is the voltage-current characteristic of a solid state deviceafter the magnitude of dynamic B+ applied to the device has beenadjusted to temporarily eliminate .a negative resistance region in thevoltage-current characteristic.

FIG. 7 is the voltage-current characteristic of a solid state deviceafter a source of dynamic B+ is applied to the device to temporarilyremove a previously formed negative resistance region and the device isformed to provide the voltage-current characteristic with a secondnegative resistance region.

FIG. 8 is the voltage-current characteristic of a solid state deviceafter a second negative resistance region has been formed and after thesolid state device has regained a first negative resistance region thatwas temporarily removed by the application of a source of dynamic 13+ tothe solid state device.

As used in the present application, dynamic B+ is defined as aperiodically varying potential applied to a selected nonlinear device tostore energy therein and to enable the device to function as anamplifier and/ or to exhibit a negative resistance characteristic. As anexample, a source of dynamic B+ may be a source of recurring signalsproviding signals having a frequency or .repetition rate greater thanthe reciprocal of the lifetime of electrical charge carriers injectedinto the variable impedance device to which the source of dynamic B+ isconnected.

In accordance with the present invention, a solid state .device isprovided Whose voltage-current characteristic has a plurality ofnegative resistance regions. .This is accomplished by applying formingenergy to an electrode of the solid state device to effect the migrationof atoms from the electrode into the body of the device and therebycreate lattice defects which establish a plurality of p-n junctions indiscrete zones in the body near the surface of the solid state device towhich the electrode is connected.

In one embodiment of the present invention, a first series of smallquantities of forming energy is applied to an electrode of the solidstate device while the voltagecurrent characteristic of the device ismonitored. The

first series is terminated when the characteristic has acquired a firstnegative resistance region at a first potential A source of dynamic B+is then applied to the solid state device and the magnitude of thedynamic B+ is adjusted to temporarily remove the first negativeresistance region. Thereafter, a second series of small quantities offorming energy at an energy level higher than the first series isapplied to the electrode. The voltagecurrent characteristic of the solidstate device is again monitored and the second series is terminated whenthe characteristic has acquired a second negative resistance region at asecond potential level. The source of dynamic B+ is then removed and thecharacteristic regains the first negative resistance region. In thisway, the solid state device is formed so that it will have avoltagecurrent characteristic that has two negative resistance regions.It is, of course, understood that the same steps may be followed toprovide the characteristic with additional negative resistance regionsat various potential levels.

Referring to FIG. 1, solid state device 10 may be selectively connectedin series with capacitors 11, 12, or 13 through switches 14 and 15.Power supply 16 may be connected across capacitors 11, 12, or 13 throughdouble pole, double throw switch 17 and switches 14 and 15. Constantcurrent sweeper 18 is connected between solid state device 10 andcathode ray tube indicator 19. The source of dynamic B+ 20 may beconnected through switch 21 and capacitor 22 across solid state device10 depending upon the position of switches 14 and 15. And, DC. powersupply 23 may be connected across solid state device 10 through switch24.

Solid state device 10 may be any device having a body of one type ofsemiconductor material and an electrode connected thereto of anothertype of semiconductor material. For example, the body may be a singlecrystal of N-type material which has been doped to give a resistivity ofohm-cm. and the electrode may be of Phosphor bronze, a material havingP-type impurities. The connection of the electrode to the body may be,for example, of the type conventionally used in point contacttransistors.

The value of capacitors 1.1, 12 and 13 and the magnitude of directcurrent voltage that is applied to these capacitors by power supply 16will depend upon the magnitude of energy that is to be applied to thesolid state device for forming purposes i.e., to move atoms from theelectrode into the body to cause lattice defects therein. The magnitudeof energy that is required is dependent on such factors as: resistivityand composition of the body of the solid state device, chemistry andcomposition of the electrode, nature of the connection between theelectrode and the body, initial surface states, history of the devicei.e., whether there has been previous forming, and the form factor ofthe energy that is applied to the solid state device. For example, ifthe solid state device has an N-type body of 5 ohm-cm. and pressurecontact between the body and a Phosphor bronze electrode, the values ofcapacitors 11, 12A, and 13 will be of the order of 1.0 ,unf., 0.01 L,and 0.001 ref, respectively, and the voltage that will be applied tothese capacitors will be of the order of 140 V. DC.

The source of dynamic B+ may be any source of recurring signals so longas the frequency or repetition rate of the recurring signals is greaterthan the reciprocal of the lifetime of the injected electrical chargecarriers, and so long as the electrode of the semiconductor device 10 towhich the forming energy is applied is driven positive with respect tothe base during each cycle of operation. In the arrangement shown inFIG. 1, a constant voltage square wave generator which has a typicalrepetition rate of 1 mc. with a 50% duty cycle is used as a source ofdynamic B+. If desired the source of dynamic B+ may be supplemented by asource of optical dynamic B+ applied to the p-n junction by a lightsource and a chopper.

.Since solid state device 10 has a body of N-type material, theelectrical charge carriers stored in the body will be holes. If solidstate device had a body of P-type material, the stored electrical chargecarriers would be electrons.

In the arrangement shown in FIG. 1, constant current sweeper 18 is aconventional constant current instrument. A constant current instrumentis used since the avalanche negative resistance region of thevoltage-current characteristic to be monitored is N-type or currentcontrolled.

In applying one embodiment of the method taught by the presentinvention, switches 21 and 24 are opened, switch 14 is placed in theupper position shown in FIG. 1, and switch 15 is positioned so thatcapacitor 13 is in series with solid state device v10. (Thevoltage-current characteristic of the solid state device, as viewed oncathode ray indicator 19, will be as shown in FIG. 2.) After doublepole, double throw switch 17 is thrown to the right hand position asshown in FIG. 1, switch 14 is positioned first to charge capacitor 13and then to apply the energy stored therein to solid state device 10. Ifthe quantity of energy applied to the solid state device has the propervalue, the device will acquire a voltage current characteristic havingthe negative resistance region XY shown in FIG. 3. The correct value ofthe quantity of energy to be applied to obtain this negative resistancecharacteristic will be dependent on such factors as: resistivity andcomposition of the body, chemistry and composition of the electrode andthe body, initial surface states, history of the device, i.e., whetherthere has been previous forming, and the form factor of the energy thatis applied to the solid state device.

If the value of the quantity of energy applied to the solid state deviceis too great, the device will acquire the voltage-current characteristic0B in FIG. 3. (This voltage-current characteristic is similar to thatobtained by present collector forming techniques in the manufacture ofpoint contact transistors.) Double pole, double throw switch 17 may thenbe reversed, i.e., thrown in the left hand position shown in FIG. 1 anda small quantity of energy applied to solid state device 10 in adirection opposite to that of the quantity of energy mentioned above.Provided that solid state device 10 has not been overformed and thequantity of energy applied in the opposite direction is of the propermagnitude, the solid state device will acquire a voltage-currentcharacteristic having a negative resistance region XY as shown in FIG.3.

Referring to FIG. 4, for a typical solid state device, one might expecta negative resistance region to appear in a voltage-currentcharacteristic located between the voltage-current characteristics ORand 0Q. If the magnitude of the quantity of energy applied to solidstate device 10 is such as to give the device a voltage-currentcharacteristic having an average impedance of less than 25K, it islikely that the device will be overformed, and it will not be possibleto obtain a negative resistance region in its voltage-currentcharacteristic by applying to the device a small quantity of energyhaving a polarity opposite to that of the initial quantity of energyapplied to the solid state device.

In applying a second embodiment of the present invention, the first stepis to close switch 21, open switch 24-, and position switches 14- and 15to connect solid state device in parallel with capacitor 13 and throwingdouble pole, double throw switch 17 in the right hand position shown inFIG. 1. The voltage-current characteristic of solid state device 10 willbe as shown in FIG. 5. The shape of the voltage-current characteristiccurve in this figure is attributed to the storage of a steady state ofelectrical charge carriers in the body of the solid state device asexplained in copending US. application Ser. No. 629,763, filed December20, 1956, entitled Electrical Switching Circuit, now Patent No.2,939,966, and in copending U.S. application Ser. No. 629,761, filedDecember 240, 1956, entitled Electrical Amplifying Circui now Patent No.2,941,094. The next step in the second embodiment is to open switch 21to remove source of dynamic B+ 20 from the solid state device and tosequentially and successively position switch 14 to charge capacitor 13and then discharge the capacitor through solid state device 10, therebyapplying a series of small quantities of forming energy to the solidstate device.

Referring to FIG. 4, as the series of small quantities of energy isapplied to the electrode, the slope of the voltage-current of the solidstate device will decrease from OP to 0Q. If the series is continued,solid state device will acquire voltage-current characteristic OT havingnegative resistance region DC. Should the series be wutinued thereafter,the negative resistance region will be lost as indicated byvoltage-current characteristic OB in FIG. 3. It may be regained,however, by reversing double pole, double throw switch 17 and applying asmall quantity of energy to the solid state device, provided that theseries of small quantities of energy is interrupted before the slope ofthe voltage-current characteristic decreases below OR. If the slopedecreases below OR, it is not likely that the negative resistance regioncould be regained by applying a small quantity of energy to solid statedevice 10 that has a polarity opposite to that of the series of smallquantities of forming energy.

After the desired negative resistance region CD is obtained, switch 21is closed to apply the source of dynamic B+ 20 to solid state device 10.The magnitude of the dynamic B+ is then adjusted to temporarily removethe negative resistance region CD of the voltage-current characteristicshown in FIG. 4. This is accomplished by incleasing the magnitude of thedynamic B+ to increase the area under the portion TV of thecharacteristic curve shown in FIG. 5 until it blankets or shields thenegative resistance portion CD of voltage-current characteristic OTshown in FIG. 4. The voltage-current characteristic shown in FIG. 6 willthen be observed on cathode ray indicator 19.

Following this operation, switch is positioned and switch 14 issequentially and successively positioned to charge capacitor 12 and thendischarge the capacitor through solid state device 10 to apply a secondseries of small quantities of energy to the solid state device. When thevoltage-current characteristic shown in FIG. 7 is observed on cathoderay tube indicator 19, the second series of small quantities of formingenergy is interrupted.

Switch 21 is then opened to remove the source of dynamic B+ from solidstate device 10. When this is done, the voltage-current characteristicof the solid state device will regain negative resistance region CD and,as shown in FIG. 8, the characteristic will have two negative resistanceregions, namely CD and EF. It is, of course, understood that the abovemethod could be used to provide the solid state device with as manynegative resistance regions as desired.

The negative resistance regions CD and EF shown in FIG. 8 are attributedto the fact that atoms of P-type material are moved from the electrodeinto the body of the solid state device by the first and second seriesof small quantities of forming energy. The atoms cause interstitial andsubstitutional lattice defects in the body to form p-n junctions inzones up to microns from the surface of the body in the area where theelectrode is connected. A zone in the body of the solid state device maybe defined on an atomic scale and may include a single atom of animpurity element or a cluster of impurity atoms located in the latticestructure of the body of the device.

Referring to FIG. 8, the potential P at which the negative resistanceregion DC will appear is dependent upon the intrinsic conductivity onthe high resistivity side of the p-n junction to which the negativeresistance region is attributed. The range over which the negativeresistance region CD extends will depend upon the number of atomsdeposited in the p region of the last mentioned p-n junction.

If desired, the voltage-current characteristic shown in FIG. 8 could beobtained without applying the source of dynamic B+ to solid state device10. The source of dynamic B+ is applied When it is desired to lower theconductivity of the base of the solid state device so that smallerquantities of energy can be applied to the solid state device to obtaina predetermined negative resistance region; or when it is desired totemporarily remove a negative-resistance region while a series of smallquantities of forming energy is applied to the solid state device toprovide the voltage-current characteristic of the same with anothernegative resistance region.

In a third embodiment of the present invention, a small quantity ofenergy having a predetermined value is applied to the electrode toprovide the solid state device with a first negative resistance regionat a first potential level. (The steps employed to accomplish this endmay be the same as those employed in the first embodiment describedabove.) The source of dynamic B+ is then applied to the solid statedevice and adjusted to the magnitude required to temporarily remove thefirst negative resistance region. (This step is the same as the onedescribed in the second embodiment for accomplishing the same end.) Asecond small quantity of energy is then applied to the electrode toprovide the solid state device with a second negative resistance level.Finally, the source of dynamic 13-]- is removed from the solid statedevice which then regains the first negative resistance region. In thisway, the voltage-current characteristic of the device is provided with afirst and second negative resistance region. It is, of course,understood that if desired the above steps could be repeated to providethe device with additional negative resistance regions.

In applying the method taught by the present invention, it is necessaryto employ a small quantity or small quantities of energy that have theproper form factor. If energy is applied to the electrode too slowly, aninsufficient number of atoms from the electrode will be deposited in thebody of the solid state device. If energy is applied too rapidly, toomany atoms will be deposited.

Thus, in FIG. 1 an arrangement is shown for controlling the timeconstant of the circuit, which in turn controls the form factor of theforming energy applied to the electrode of solid state device 10. Themagnitude of the impedance of solid state device 10 may be controlled bythe bias applied to the solid state device. This together with theselected values of capacitors 11, 12, and 13 and the selected magnitudeof the voltage applied to these capacitors will determine in part thetime constant of the circuit and the form factor of the energy appliedto solid state device 10. Hence, in the arrangement shown in FIG. 1, theform factor of the energy applied to the electrode can be controlled byclosing switch 24 and adjusting the plus or minus bias applied by DC.power supply 23 to solid state device 10.

Various modifications are contemplated and may obviously be restorted toby those skilled in the art without departing from the spirit and scopeof the invention as hereinafter defined by the appended claims, as onlya preferred embodiment thereof has been disclosed.

What is claimed is:

1. A solid state device comprising a body of a first type ofsemiconductor material in which particles of a second type ofsemiconductor material have been locally dispersed in the crystallattice thereof, and an electrode connected to said body.

2. A solid state device comprising a body of a first type ofsemiconductor material in which particles of a second type ofsemiconductor material have been dispersed in discrete zones in thecrystal lattice, and an electrode connected to said body.

3. A solid state device comprising a body of semiconductor materialhaving a plurality of p-n junctions which break down at differentpotential levels and which are located in discrete zones in the crystallattice and an electrode connected to said body.

4. A solid state device comprising a body of semiconductor materialhaving a resistivity of the order of 5 ohm-cm. in which particles of asecond type of semiconductor material have been dispersed in discretezones 7 in the crystal lattice to establish p-n junctions, and anelectrode Connected to said body.

5. A solid state device comprising a body having a first surface and asecond surface, said body consisting of semiconductor material having aresistivity in the order of ohm-cm. in which particles of another typeof semiconductor material have been dispersed in discrete zones in thecrystal lattice to establish p-n junctions in distances up toapproximately 25 microns from said first surface, and an electrodeconnected to said first surface.

6. The method of forming a solid state device having a semiconductorbody and an electrode connected to said body, which comprisessuccessively applying each of a plurality of series of small quantitiesof forming energy to said electrode, each of said series being atdifierent energy levels, applying high frequency energy to said body,monitoring the voltage-current characteristic of said solid statedevice, interrupting the application of each of said series when saidvoltage-current characteristic has acquired -a desired negativeresistance region, each negative resistance region occurring at adifferent potential level, and increasing the magnitude of highfrequency energy applied to said body after the application of eachseries of small quantities of forming energy to shield the negativeresistance region formed by the preceding series while a succeedingseries is applied.

7. The method of forming a solid state device having a selectedvoltage-current characteristic and including a semiconductor and anelectrode connected to said body, which comprises applying formingenergy having a first selected level in small successive quantities tosaid electrode until said voltage-current characteristic acquires afirst negative resistance region, applying high frequency energy to saidelectrode having a magnitude such that said first negative resistanceregion is shielded, applying forming energy having a second selectedlevel in small successive quantities to said electrode until saidvoltage-current characteristic acquires a second negative resistanceregion, said first and second negative resistance regions occurring atdifierent potential levels, and removing said high frequency energy fromsaid electrode.

8. The method of forming a solid state device having a desiredvoltage-current characteristic and including a semiconductor body and afirst and second electrode connected to said body, which comprisessuccessively applying each of a plurality of series of forming pulses tosaid first electrode, applying a series of alternating potential pulsesto the first electrode such that the first electrode is driven positivewith respect to the second electrode during each cycle of operation,whereby minority charge carriers are injected into said body, saidseries of alternating pulses being so closely spaced that the number ofminority charge carriers injected by a pulse in said series does notdecrease substantially before the next pulse of said series is appliedto said first electrode, interrupting the application of each series ofsaid plurality of series of forming pulses when said voltage-currentcharacteristic acquires a desired negative resistance region at aselected potential level, and varying the spacing in said series ofalternating pulses after the application of each series of formingpulses, thereby temporarily removing the negative resistance regionformed by the preceding series of forming pulses while a succeedingseries of forming pulses is being applied.

References Cited in the file of this patent or the original patentUNITED STATES PATENTS 2,476,989 Martinet et al. July 26, 1949 2,497,649Amsden Feb. 14, 1950 2,577,803 Pfann Dec. 11, 1951 2,615,965 Amico Oct.28, 1952 2,746,121 Anderson May 22, 1956 2,755,536 Dickinson July 24,1956 2,792,537 Martin May 14, 1957 2,836,521 Longini May 27, 1958

